1. Field of the Invention
The present invention relates to a method of manufacturing a liquid crystal display device (LCD) and more particularly, the present invention relates to a method of manufacturing an LCD in which a pixel electrode is formed on a photosensitive passivation layer.
2. Description of the Background Art
Generally, a conventional liquid crystal display device in which a pixel electrode is formed on a photosensitive passivation layer includes a gate bus line 60 and a data bus line 70 which are arranged in a matrix array, as shown in FIG. 1. At the end portions of the gate bus line 60 and the data bus line 70, a gate pad 60c and a data pad 70c connected to an output of a driving IC are formed, respectively. The LCD further includes a TFT which functions as a switching element and is driven by an electrical signal from the gate bus line 60 and the data bus line 70. The TFT is disposed at the intersection portion of the gate bus line and data bus line. The LCD also includes a pixel electrode 40 connected to the TFT.
The TFT includes a gate electrode 60a derived from the gate bus line 60, a source electrode 70a derived from the data bus line 70 and a drain electrode 70b arranged to face the source electrode 70a. The gate electrode 60a is covered by a gate insulating layer (not shown). A semiconductor layer 90 is disposed over the gate electrode 60a on the gate insulating layer. The source electrode 70a and the drain electrode 70b are disposed at each side of the semiconductor layer 90. The drain electrode 70b is connected to the pixel electrode 40 through a contact hole 30a formed at a passivation layer (not shown). At the overlapped portion of the adjacent gate bus line 70, a storage capacitance electrode 35 is connected to the pixel electrode 40 through a storage contact hole 30b. 
Referring to FIG. 2 which is a cross-sectional view of FIG. 1 cut along line Axe2x80x94A in FIG. 1, the structure and method of manufacturing of the LCD in which a pixel electrode is formed on the photosensitive passivation layer will be explained in detail.
On a transparent substrate 10, a gate bus line 60, a gate electrode 60a derived from the gate bus line 60 and a gate pad 60b disposed at the end of the gate bus line 60 are formed. A gate insulating layer 50 including SiNx or SiOx is formed so as to cover the entire surface of the substrate including the gate bus line 60, the gate electrode 60a and the gate pad 60b. An island-shaped semiconductor layer 90 including a-Si (amorphous silicon) is formed on the gate insulating layer 50 over the gate electrode 60a. Ohmic contact layers 90a and 90b including n+ type a-Si are formed separately on the semiconductor layer 90. A source electrode 70a and a drain electrode 70b are connected to the ohmic contact layers 90a and 90b, respectively. A data bus line 70 connected to the source electrode 70a is formed on the gate insulating layer 50. A TFT is completed by forming the gate electrode 60a, the semiconductor layer 90, the ohmic contact layers 90a and 90b, the source electrode 70a and the drain electrode 70b. 
A passivation layer 80 including a photosensitive acrylic resin is formed on the entire surface of the substrate having the TFT. A drain contact hole 30a, a storage contact hole 30b (FIG. 1) and a gate pad contact hole 30c are formed by patterning the passivation layer 80. The method of forming the contact holes includes the steps of exposing the photosensitive passivation layer with a mask, developing the passivation layer with a developer and removing the remaining passivation layer material at the contact holes with an etchant which is CF4+O2 or SF6+O2 gas. At the same time, some portions of the gate insulating layer 50 covering the gate pad 60b are removed to form a gate pad contact hole 30c exposing the gate pad 60b by using the CF4+O2 or SF6+O2 gas.
After the contact holes are formed, a pixel electrode 40 and a gate pad terminal 40a are formed by depositing an ITO (Indium Tin Oxide) on the entire surface of the substrate and then patterning the ITO layer.
The reason for using the photosensitive material for the passivation layer is that the manufacturing process is simplified because a photo resist is not used and the contact hole can be formed by etching the passivation layer directly.
In above mentioned conventional method, the surface of the passivation layer is not smooth and uniform because it is attacked by the CF4+O2 or SF6+O2 etching gas. As a result of the etching gas attacking the passivation layer surface, the pixel electrode formed on the uneven surface of the passivation layer has an undesired, uneven shape. Furthermore, when the remaining passivation layer and the gate insulating layer are removed to form a gate contact hole with the CF4+O2 or SF6+O2 etching gas, the drain electrode can be cut off as shown in region F of FIG. 2, or the gate pad and the gate insulating layer can be over-etched as shown in region G of FIG. 2.
According to the conventional method, the metal layer disposed under the passivation layer can be cut off or over-etched by the CF4+O2 or SF6+O2 etching gas, when the passivation layer is patterned so that the quality of the LCD becomes inferior.
In order to overcome the problems in the conventional methods described above, preferred embodiments of the present invention provide a method of manufacturing an LCD in which a passivation layer including a photosensitive acrylic resin has a smooth, even surface after the passivation layer is patterned and a metal layer under a passivation layer including a photosensitive acrylic resin is not cut off. In addition, preferred embodiments of the present invention provide a method of manufacturing an LCD in which a gate pad and a gate insulating layer are not over-etched when the gate insulating layer is patterned to form a gate contact hole.
To solve the above-described problems with the conventional methods and to achieve the results described in the preceding paragraph, preferred embodiments of the present invention provide a method of manufacturing an LCD using an etching gas including one of CF4+H2, CxFy+H2, CxFy+CxFyHz, CxFy+CxFyHz+H2 and CxFyHz. The method according to preferred embodiments of the present invention includes the steps of forming on a substrate, a switching element, bus lines connected to the switching element and pads at the end of each of the bus lines, coating a photosensitive passivation layer on an entire surface of the substrate, forming contact holes exposing an electrode and a pad by exposing and developing the passivation layer such that a portion of the passivation remains, removing a remaining portion of the passivation layer at the contact hole using an etching gas including at least one of CF4+H2, CxFy+H2, CxFy+CxFyHz, CxFy+CxFyHz+H2 and CxFyHz and forming a pixel electrode connected to the exposed electrode through the contact hole.
Other advantages, features and novel elements of preferred embodiments of the present invention will become apparent from the following description of preferred embodiments of the present invention with reference to the drawing figures attached hereto.